1. Field of the Invention
The present invention relates to sense amplifiers used in a programmable logic device (PLD) to implement wide or multiple input NOR gates. More particularly, the present invention relates to circuitry for a zero-power sense amplifier responsive to a sleep mode signal to reduce power consumed by the zero-power sense amplifier during the sleep mode.
2. Description of the Prior Art
Prior Art PLD Utilizing a Sense Amplifier
FIG. 1 shows an array structure for a typical prior art programmable array logic (PAL) device, a type of PLD which utilizes a sense amplifier to implement a multiple input NOR gate. The PAL of FIG. 1 has six inputs I.sub.0-5 and four outputs O.sub.0-3. The inputs I.sub.0-5 each have a true output 104 and a complement output 106 forming rows connected to programmable array cells, such as 110, of programmable array cells 108. An array cell, such as cell 110, may be programmed to be connected or disconnected to an AND gate in the AND array 100. Groups of array cells connected to an AND gate in AND array 100, such as shown at 112, are called a product term. The AND array 100 is followed by an OR array 102 to provide a sum of products term output. The OR array may be connected to an output logic macrocell 114 which is programmable to be either registered or combinatorial. Circuitry similar to that shown in FIG. 1, including the output logic macrocell 114, is utilized on the AmPALCE22V10, a device manufactured by Advanced Micro Devices, Inc.
Sense amplifiers are utilized by manufacturers to implement the AND gates in the AND array 110. The AND gates are implemented using multiple input NOR gates with true and complement row connections to array cells reversed internally. The sense amplifiers are utilized to implement the multiple input NOR gates to provide sufficient output voltage to the OR gate array 102 at high speed. Sense amplifiers convert a small voltage from the product term into a larger, rail to rail, voltage to supply to an OR gate.
Prior Art Sense Amplifier
FIG. 2 shows components of a sense amplifier 200 used to implement the multiple input NOR gate on a PLD, such as the AmPALCE22V10. The sense amplifier 200 of FIG. 2 is also shown connected to array cells 202, similar to array cells 108 of FIG. 1, to receive a single product term, such as 112 of FIG. 1. Array cells 202 of FIG. 2 receive input signals from rows 1-3 and are connected to form a product term (PT) line connection to sense amplifier 200. The array cells have lines connected to form a product term ground (PTG) line connection to sense amplifier 200.
In operation, the PT line will be high if all of the cells are off, or not conducting. The PT line will be low if one or more cells are on, or conducting. A cell will conduct if it is programmed and if its associated row line is high.
The sense amplifier 200 includes an amplifier consisting of two inverters 204 and 205. The first inverter 204 includes an p-channel pull up transistor 206 and an n-channel pull down transistor 208. The second inverter 205 includes a p-channel pull up transistors 210 and an n-channel pull down transistor 212. The input of the first inverter 204 forms the amplifier input which is further connected to the PT line of the array cells 202. The circles on transistors, such as on transistors 206 and 210, indicate a P-type transistor, while no circle on a transistor indicates an N-type transistor.
The sense amplifier 200 additionally includes a voltage clamp consisting of transistors 214 and 216. The voltage clamp 214, 216 provides feedback from the input of the second inverter 205 to the input of the first inverter 204. The clamp 214, 216 is provided since the PT line has a high capacitance due to the number of cells connected to it. With the high capacitance of the PT line, by limiting the voltage swing to small displacements around the threshold of the amplifier utilizing the clamp 214, 216 higher speeds are provided.
Further included in sense amplifier 200 is a current source transistor 218 controlled by a voltage reference VBSPRF to supply current at the PT line connection to the amplifier input. A PTG current sink transistor 220 controlled by a voltage reference VSARF1 is connected to the PTG line connection to the array cells 202.
In operation, when all cells are off, the current source 218 will provide current to pull the PT line up until node 250 is driven sufficiently low so that current sunk by clamp transistor 216 just balances the current sourced by current source 218. A low at node 250 will result in a high at SAOUT by means of inverter 205.
When one or more cells turn on, the PT line will be pulled low. The PTG current sink transistor 220 will then function as a current sink. Reference voltage VSARF1 is a current limiting voltage such that the PTG current sink transistor 220 can sink more current than sourced by current source transistor 218. Clamping is provided during turn on so that the PT line voltage will drop until node 250 is sufficiently high that clamp transistor 214 will source just enough current to balance the excess sink capacity of the PTG current sink transistor 220. Again, clamping limits the voltage swing to small displacements around the threshold of the amplifier to provide higher output switching speeds.
With the sense amplifier 200 of FIG. 2, performance is limited by the effectiveness of the clamp 214, 216 to limit the voltage swing of the PT line, as well as the slew-rate of the PT line. The slew-rate of the PT line is proportional to the non-equilibrium current driving the product term and inversely proportional to the capacitance of the PT line.
Prior Art Zero-Power Parts
With the introduction of notebook computers and other devices utilizing battery power, electronic circuits in the devices are required to utilize as little power as possible to preserve the batteries for an extended period of time. Even with devices which are not battery powered, it is desirable to have electronic circuits which operate with as little power consumption as possible to conserve energy, thus reducing operational costs.
Manufacturers have developed specialized electronic parts, called zero power parts, for use in battery powered devices such as notebook computers. The zero power parts have a low power consumption mode, also referred to as a sleep mode, which is entered when the zero power part has not been accessed for a period of time. To create the sleep mode, a sleep mode signal is developed by circuitry in the zero-power part and is transmitted in a true state to turn off internal components of the zero power part when an input signal has not been received for a period of time. The sleep mode signal is transmitted in a complement state to power up, or wake up the internal components of the zero-power part from a sleep mode when another input signal to the zero-power part is received.
For the AmPALCE22V10 discussed above, a zero power version, the AmPALCE22V10Z-25, is also available from Advanced Micro Devices, Inc. The AmPALCE22V10Z-25 operates at a lower speed because the AmPALCE22V10 does not require time to be powered up from a sleep mode.
Prior Art Zero-Power Sense Amplifier
The AmPALCE22V10Z-25 includes a zero-power sense amplifier to implement a multiple input NOR gate. A zero-power sense amplifier differs from a standard sense amplifier in that it includes zero-power circuitry connected to reduce power consumption during a sleep mode. During a sleep mode, the zero-power sense amplifier will draw negligible power.
In prior art zero-power sense amplifiers, the zero-power circuitry connected to the sense amplifier placed the output of the sense amplifier, SAOUT, in one state, usually a low state, independent of the state of the input signal on the PT line prior to a sleep mode being entered. When a signal was received by the zero-power sense amplifier to power up, the zero-power circuitry enabled the zero-power sense amplifier to power up and to obtain an output required by the current input signal after a recovery time period.
The performance of a zero-power sense amplifier is measured by how quickly the zero-power sense amplifier can recover from a sleep state and respond to a changing input signal.